1. Field of the Invention
The present invention relates to a semiconductor device in which an active region is formed by a semiconductor film having a crystalline structure. In particular, the present invention relates to a semiconductor device in which a thin film transistor is formed, or in which a circuit is formed by thin film transistors. Note that, in this specification, the term semiconductor device indicates general devices which can function by utilizing semiconductor characteristics, and that semiconductor integrated circuits, electro-optical devices, and electronic devices are all included in the category of semiconductor devices.
Note also that, throughout this specification, the term semiconductor device indicates general devices which can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.
2. Description of the Related Art
Techniques of using a semiconductor film (hereinafter referred to as crystalline semiconductor film) having a crystalline structure on the order of several nm to several hundreds of run in thickness formed on a substrate having an insulating surface in order to form thin film transistors (hereafter referred to as TFTs) have been developed. TFTs are being put into practical use as switching elements for liquid crystal display devices, and in recent years it has become possible to form a semiconductor integrated circuit on a glass substrate.
Silicon is mainly used as the material for crystalline semiconductor films used in TFTs. A silicon film having a crystalline structure (hereafter referred to as a crystalline silicon film) utilizes an amorphous silicon film deposited on a substrate, such as glass or quartz, by plasma CVD or low pressure CVD, which is then crystallized by heat treatment or laser light irradiation (hereafter referred to as laser processing throughout this specification).
However, it is necessary to heat the amorphous silicon film to a temperature equal to or greater than 600xc2x0 C. for 10 or more hours in order to crystallize the amorphous semiconductor film if crystallization is performed by heat treatment. The processing temperature and processing time cannot necessarily be thought of as suitable when considering the productivity of TFTs. It also becomes necessary to use a large size heat treatment furnace in order to handle substrates which have large surface areas when considering a liquid crystal display device as an applied product using the TFTs, and not only does the energy consumed during the process of manufacturing increase greatly, but it also becomes difficult to obtain uniform crystals across a wide surface area. Further, if laser processing is used, it is also difficult to obtain homogeneous crystals if laser processing is used because the output of laser oscillators is unstable. This type of dispersion in the quality of crystals becomes a cause of dispersion in the properties of the TFTs, and there is a fear that this will be a factor in lowering the display quality of a liquid crystal display device or an EL display device.
On the other hand, techniques have been developed for manufacturing a crystalline semiconductor film by introducing a metal element for promoting the crystallization of silicon into an amorphous silicon film, and then using heat treatment at a temperature lower than that conventionally used. For example, Japanese Patent Application Laid-open Nos. Hei 7-130652 and Hei 8-78329 disclose that a metal element such as nickel is introduced into an amorphous silicon film, and a crystalline silicon film is obtained by heat treatment for 4 hours at 550xc2x0 C.
Furthermore, TFTs using crystalline silicon films thus manufactured are still inferior compared to the characteristics of MOS transistors using a single crystal silicon substrate. Even if semiconductor films, having thickness of several nm to several hundreds of nm and formed on various materials such as glass and quartz, are crystallized, only polycrystalline structures made from an aggregate of a plurality of crystal grains can be obtained. Carriers become trapped due to a plurality of defects existing in the crystal grains and in the crystal grain boundaries, and this causes restrictions in the TFT performance.
However, the crystal orientation planes exist randomly for crystalline silicon films manufactured by the above conventional method, and the orientation ratio with respect to a specified crystal orientation is low. Crystalline silicon films obtained by heat treatment or laser processing have a plurality of crystal grains deposited, with a tendency to be oriented in the {111} plane. However, the ratio of this orientation toward the plane orientation does not exceed 20% of the total.
If the orientation ratio is low, then it may be assumed that it becomes almost impossible to maintain continuity of the lattice at crystal grain boundaries in which crystals having differing orientations meet to generate a plurality of unpaired bonding sites. Unpaired bonding sites occurring at the grain boundaries become centers, which capture carriers (electrons, holes), thereby lowering the transport characteristics. Namely, the carrier is dispersed and trapped, and therefore a TFT having high electric field effect mobility cannot be expected when the TFT is manufactured from this type of crystalline semiconductor film. Further, the crystal grain boundaries exist randomly, and therefore it is impossible to form a channel-forming region by crystal grains possessing a specified crystal orientation. This becomes a cause of dispersion in the TFT electrical properties.
An object of the present invention is to provide a means of solving these types of problems, and an object of the present invention is to increase the orientation of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film, and to provide a TFT, which uses this type of crystalline semiconductor film in an active layer.
The distribution of crystal orientation is found in accordance with EBSP (electron backscatter diffraction patterning). EBSP is a method (hereafter referred to as EBSP method, for convenience) of analyzing crystal orientation from the backscatter of primary electrons using a specialized detector formed in a scanning electron microscope (SEM). In this specification, S-4300SE scanning electron microscope of Hitachi Science Systems Co. Ltd. is used as the scanning electron microscope, and xe2x80x9cOrientation Imaging Microscopyxe2x80x9d of TSL Co. Ltd. is used as the specialized detector. A method of measuring by the EBSP method is explained in accordance with FIG. 6. An electron gun (a Schottky field emission electron gun) 101, a mirror 102, and a test piece chamber 103 have the same structure as those of a normal scanning electron microscope. A stage 104 is formed having an inclination on the order of 60xc2x0 for measuring EBSP, and a sample 109 is set thereupon. A screen 105 of a detector 106 is inserted in this state so as to face the test piece.
If an electron beam is irradiated to a test piece having a crystalline structure, inelastic scattering occurs in back, and a linear pattern unique to the crystal orientation within the test sample by Bragg diffraction (generally referred to as a Kikuchi image) is observed. The crystal orientation of the test sample is found by analyzing the Kikuchi images shown in the detector screen with the EBSP method.
FIG. 7 shows a crystalline semiconductor film 122, having a polycrystalline structure, formed on a substrate 121. The polycrystalline structure is assumed to possess crystal grains each having different crystal orientations. By repeatedly moving the position at which the electron beam strikes the test piece and analyzing the orientation (mapping measurement), the crystal orientation, or arrangement information, of the planer shape test piece can be obtained. The thickness of the imparted electron beam differs depending upon the type of the electron gun of the scanning electron microscope, but for Schottky field emission type, an extremely fine electron beam 123 having a spot diameter of 10 to 20 nm is irradiated. With mapping measurement, very averaged information for the crystal orientation can be obtained as the number of measurement points increases, or as the measurement region is expanded. In practice, measurement is performed in a 100xc3x97100 xcexcm2 region with on the order of 10,000 (1 xcexcm spacing) to 40,000 (0.5 xcexcm spacing) points.
If all of the crystal orientations of each crystal grain are found by mapping measurement, then the state of crystal orientation with respect to the film can be displayed statistically. An example of an inverse pole diagram found by EBSP is shown in FIG. 8A. Inverse pole diagrams are often used when displaying the precedence of orientations of a polycrystalline body, and therefore collective display of which lattice plane coincides with a certain specific plane of the test piece (the film surface here) can be performed.
The fan shaped frame of FIG. 8A is generally referred to as a standard triangular shape, and therefore all of the indices of a cubic crystal system are contained within. Further, the lengths occurring within the figure correspond to the angle in the crystal orientation. For example, the angle between {001} and {101} is 45xc2x0, the angle between {101} and {111} is 35.26xc2x0, and the angle between {111} and {001} is 54.74xc2x0. Further, the white dashed line shows a range in which there is a difference of 5 to 10xc2x0 from {101}.
FIG. 8A is a diagram in which all points measured in mapping (11,655 points with this example) are plotted within the standard triangular shape. It can be seen that the density of points in the vicinity of {101} is high. FIG. 8B is a diagram showing contour lines for the intensity of such points. The numerical values here are non-dimensional numerals showing a multiplier for a case in which it is assumed that each crystal grain has a completely random orientation, in other words, that the points inside the standard triangular shape are distributed without bias.
If the orientation precedence is known to be a specific index ({101} here), then it becomes very easy to image the degree or orientation precedence by quantifying the ratio of how many crystal grains have gathered in the vicinity of the index. For example, in the inverse pole diagram shown in FIG. 8A, the ratio of the number of points existing within a range (the white dashed line in the figure) having a difference of 5 to 10xc2x0 with {101} to the whole can be found as an orientation ratio in accordance with the following equation.
{101} orientation ratio=(measurement points within allowable error of an angle between {101} lattice plane and film surface)/(the number of all measurement points)
This ratio can also be explained as follows. If the distribution aggregates in the vicinity of {101} plane, as in FIG. 8A, then the  less than 101 greater than  direction of each grain is almost perpendicular to the substrate with an actual film, as in FIG. 10, but the grains are expected to be lined up possessing a slight wavering in the periphery. The tolerance of the difference angle is set to 5xc2x0 and 10xc2x0, and the ratio of values smaller than those are shown by the numerical values. For example, in FIG. 9 the  less than 101 greater than  direction of a certain crystal grain is included in the 10xc2x0 tolerance, although it does not fall within the 5xc2x0 tolerance. For the latter data, the tolerance angle is set to 5xc2x0 or is set to 10xc2x0, and the ratio of crystal grains satisfying the tolerance is displayed, as explained above.
An invention structure disclosed in this specification is characterized in a semiconductor device comprising a thin film transistor having: a semiconductor layer containing a channel-forming region; a source region; and a drain region on an insulating film covering an electrode;
wherein:
the channel-forming region: has silicon as its main constituent and contains germanium; has a concentration of nitrogen, and a concentration of carbon, less than 5xc3x971018/cm3 as detected by secondary ion mass spectroscopy; and has a concentration of oxygen less than 1xc3x971019/cm3 as detected by secondary ion mass spectroscopy;
the channel-forming region is made from a semiconductor film containing a plurality of crystal grains; and
the ratio, within a plurality of crystal planes in the channel-forming region, of the crystal planes which form an angle equal to or less than 10xc2x0 with a substrate surface, measured by a method of reflective electron beam diffraction patterning while moving the position at which an electron beam strikes, is as follows:
greater than or equal to 20% when the crystal plane is {101};
less than or equal to 3% when the crystal plane is {001}; and
less than or equal to 5% when the crystal plane is {111}.
In the above structure, the channel-forming region comprises silicon and germanium, and a concentration of germanium is larger than or equal to 0.1 atom %, and less than or equal to 10 atom %.
Further, in the above structure, the electrode comprises a gate electrode, the insulating film comprises a gate insulating film, and the thin film transistor is a reverse stagger type thin film transistor. It should be noted that the channel-forming region in this specification denotes a region (called xe2x80x9cchannelxe2x80x9d) in which carriers are transported. In case of a reverse stagger type thin film transistor, for example, the channel is formed in a vicinity of an interface between the semiconductor film and the gate insulating film over the gate electrode. However, a whole region of the semiconductor film including the interface is called the channel-forming region.
Further, in the above structure, the semiconductor layer is obtained by a heat treatment or by a laser processing to an amorphous semiconductor film provided with a metal element. After the laser processing, a light from a halogen lamp, a xenon lamp, a mercury lamp, or a metal halide lamp may be irradiated to the crystallized semiconductor film.
Further, in the above structure, the metal element may be one or a plurality of elements selected from the group consisting of Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. And it is preferable to reduce a concentration of the metal element contained in the crystallized semiconductor film at less than 1xc3x971017 atoms/cm3 by a gettering process.
Further, in the above structure, the channel-forming region has a germanium concentration gradient in which the germanium concentration becomes larger with increasing a distance from an interface with said insulating film in the film thickness direction. FIGS. 13A to 13C are graphs which show germanium concentration gradient when the semiconductor layer comprising silicon and germanium is treated by a heating or laser processing. FIG. 13A shows a SIMS data for a test piece in which the semiconductor film provided with Ni of 10 ppm is heat treated at 550xc2x0 C. for 4 hours. FIG. 13B shows a SIMS data after the test piece of FIG. 13A is further treated by a laser irradiation at 471 mJ/cm2. FIG. 13C shows a SIMS data after the test piece of FIG. 13A is further treated by a laser irradiation at 521 mJ/cm2.
Further, in the semiconductor device comprising a pixel portion and a driver circuit formed over a same substrate, all thin film transistors in the pixel portion and the driver circuit may be formed of reverse stagger type n-channel thin film transistors. And semiconductor layers in these thin film transistors have large orientation ratio in {101} lattice plane.
Further, in the semiconductor device comprising a pixel portion and a driver circuit formed over a same substrate, all thin film transistors in the pixel portion and the driver circuit may be formed of reverse stagger type p-channel thin film transistors. And semiconductor layers in these thin film transistors have large orientation ratio in {101} lattice plane.
Further, in the semiconductor device comprising a pixel portion and a driver circuit formed over a same substrate, all thin film transistors in the pixel portion and the driver circuit may be formed of reverse stagger type n-channel thin film transistors or p-channel thin film transistors. And semiconductor layers in these thin film transistors have large orientation ratio in {101} lattice plane.
Further, in the semiconductor device comprising a pixel portion formed over a same substrate, semiconductor layers in of thin film transistors in the pixel portion are formed on an insulating film covering an electrode. And the semiconductor layers in these thin film transistors have large orientation ratio in {101} lattice plane.
Further, in the above structure, a difference between an interval of lattice planes which is horizontal to the semiconductor layer and an interval of lattice planes which is oblique by 60xc2x0 is exceeding 0 and less than or equal to 0.002 nm calculated in lattice constant.